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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-12521-3E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89910 Series
MB89913/915/P915/PV910
s DESCRIPTION
The MB89910 series has been developed as a general-purpose version of the F2MC*-8L family consisting of proprietary 8-bit, single-chip microcontrollers. In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, timers, a serial interface, an A/D converter, a buzzer output, a low-voltage detection reset, high-voltage driver, a watch prescaler, and external interrupts. The MB89910 series is applicable to a wide range of applications from consumer products to industrial equipments. *: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Minimum execution time: 0.50 s/8.0 MHz oscillation * Interrupt processing time: 4.50 s/8.0 MHz oscillation * F2MC-8L family CPU core Multiplication and division instructions 16-bit arithmetic operations Test and branch instructions Bit manipulation instructions, etc.
Instruction set optimized for controllers
* Dual-clock control system
(Continued)
s PACKAGE
48-pin Plastic SH-DIP 48-pin Plastic QFP 64-pin Ceramic MDIP
(DIP-48P-M01)
(FPT-48P-M15)
(MDP-64C-P02)
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MB89910 Series
(Continued) * High-voltage ports (built-in a pull-down resistor capable) 8 ports for large current 10 ports for small current * 8-bit PWM timer: 1 channel * 16-bit timer/counter: 1 channel * 21-bit timebase timer * 8-bit serial I/O: 1 channel * 8-bit A/D converter: 8 channels * External interrupt Edge detection function Two channels, including one of which voltage can be applied from -0.3 to +7.0 V * Low-voltage detection reset (excluding the MB89PV910) * Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode) * Reset output and power-on reset function * Watch prescaler
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MB89910 Series
s PRODUCT LINEUP
Part number Parameter Classification Mass production product (mask ROM product) ROM size 8 K x 8 bits (internal mask ROM) 16 K x 8 bits (internal mask ROM) One-time PROM product MB89913 MB89915 MB89P915 MB89PV910 Piggyback/ evaluation product (for evaluation and development)
16 K x 8 bits 32K x 8 bits (internal PROM, (Piggyback) programmable with (External ROM) general-purpose EPROM programmer) 1 K x 8 bits
RAM size CPU functions
256 x 8 bits Number of instructions: Instruction bit length: Instruction length: Data bit length: Minimum execution time: Interrupt processing time:
512 x 8 bits
136 8 bits 1 to 3 bytes 1, 8, 16 bits 0.50 s/8.0 MHz to 8.00 s/8.0 MHz, or 61 s/32.768 kHz 4.5 s/8.0 MHz to 72.0 s/8.0 MHz, or 549.3 s/32.768 kHz Note: The above times depend on the gear function.
Ports
High-voltage output ports (P-ch open-drain): 8 (P10 to P17 for large current) 10 (P20 to P27 and P50 to P51 for small current) I/O ports (CMOS): 13 (P00 to P07, P34 to P37, and P40) I/O ports (N-ch open-drain): 6 (P30 to P33, P41, P42) Input ports (CMOS): 2 (P60 and P61 also serve as a subclock pin) Total: 39 Capable of generating four different intervals at 8.0-MHz oscillation: 0.26, 0.51, 1.02, and 524.0 ms
Timebase timer (Timer 1)
8-bit PWM timer (Timer 2) 8-bit timer operation (square wave output capable. Operation clock: 1, 2, 8, or 16 instruction cycles) 8-bit resolution PWM operation (Conversion cycle: 128 s to 2.0 ms at 8.0 MHz) 16-bit timer/counter (Timer 3) 8-bit serial I/O 16-bit timer operation (operating clock: 1 instruction cycle) 16-bit event counter operation (Rising/falling/both edges selectable) 8 bits LSB first/MSB first selectable Transfer clock (external, 4/8/16 instruction cycles) 8-bit resolution x 8 channels A/D conversion mode (conversion time of 22.0 s/8.0 MHz) Sense mode (conversion time of 6.0 s/8.0 MHz) Continuous activation enabled by external clock or internal clock Reference voltage input (AVR) is provided.
8-bit A/D converter
(Continued)
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MB89910 Series
(Continued)
Part number Parameter External interrupt MB89913 MB89915 MB89P915 MB89PPV910
2 independent channels (edge selection, interrupt vector, factor flag) Rising/ falling/both edges selectable Built-in analog noise canceller Used also for wake-up stop/sleep modes. (Edge detection is also permitted in stop mode.) Continuous operation (detection power supply voltage of 4.00.3 V, 3.60.3 V or 3.30.3 V) Intermittent operation (Activated for each watch interrupt under the dual-clock system) Sleep mode, stop mode, and watch mode CMOS 3.8 V to 5.5 V 4.5 V to 5.5 V MBM27C256A-20CZ Not available
Low-voltage detection reset
Low-power consumption (Standby mode) Process Operating voltage* EPROM for use
* : Varies with conditions such as the operating frequency. (See section "s Electrical Characteristics.") In the case of the MB89PV910, the voltage varies with the ICE or the EPROM to be connected.
s PACKAGE AND CORRESPONDING PRODUCTS
Package DIP-48P-M01 FPT-48P-M15 MDP-64C-P02 : Available x: Not available x *1 MB89913 MB89915 MB89P915 MB89PV910 x x *2
*1: Under examination for development *2: Available by conversion from MDIP-64 to SH-DIP-48 64SD-48SD-8L2: For conversion (MDP-64C-P02) DIP-48P-M01 Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Note: For more information about each package, see section "s Package Dimensions."
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MB89910 Series
s DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used. Take particular care on the following points: * The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
* In the case of the MB89PV910, add the current consumed by the EPROM which is connected to the top socket. * When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume more current than the product with a mask ROM. However, the current consumption in sleep/stop modes is the same. (For more information, see sections "s Electrical Characteristics" and "s Example Characteristics.")
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product. Before using options check section "s Mask Options." Take particular care on the following points: * A pull-down resistor for P10 to P17, P20 to P27, and for P50 to P51 cannot be set for the MB89P915 and MB89PV910. The MB89915 and MB89913 allow a pull-down resistor to be set for individual pins. Such pins on the MB89P915 and MB89PV910 are fixed to have no pull-down resistor. * The low-voltage detection reset cannot be used on the MB89PV910. The voltage to be detected by the lowvoltage detection reset is set by using a register for the MB89P915 and by using a mask option for the MB89915 and MB89913. If the detection voltage has been set to a lower value than the operating voltage, however, use the gear function to operate the device with the faster clock at a lower speed, or operate the device with the slower clock. Note that the results of operation are unpredictable if the device is attempted to operate at a lower voltage than the operating voltage with the faster clock put in top gear.
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MB89910 Series
s PIN ASSIGNMENT
(Top view)
AVSS AVR P37/AN7 P36/AN6 P35/AN5 P34/AN4 P33/AN3 P32/AN2 P31/AN1 P30/AN0 P07/SCK P06/SO P05/SI P04/PWO P03/EC P02/ADST P01/BZ2 P00 P61/X1A P60/X0A P42 P41/INT1 P40/INT0 RST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (DIP-48P-M01)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VCC P10 P11 P12 P13 P14 P15 P16 P17 VFDP P20 P21 P22 P23 P24 P25 P26 P27 P50 P51/BZ1 TEST X1 X0 VSS
(Top view) P34/AN4 P35/AN5 P36/AN6 P37/AN7 AVR AVSS VCC P10 P11 P12 P13 P14 P33/AN3 P32/AN2 P31/AN1 P30/AN0 P07/SCK P06/SO P05/SI P04/PWO P03/EC P02/ADST P01/BZ2 P00 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
Under examination for development
P15 P16 P17 VFDP P20 P21 P22 P23 P24 P25 P26 P27
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X1A/P61 X0A/P60 P42 P41/INT1 P40/INT0 RST VSS X0 X1 TEST P51/BZ1 P50 (FPT-48P-M15)
13 14 15 16 17 18 19 20 21 22 23 24
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MB89910 Series
(Top view) VCC P10 P11 P12 P13 P14 P15 P16 P17 VFDP P20 P21 P22 P23 P24 P25 P26 P27 P50 P51/BZ1 TEST X1 X0 VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C.
AVSS AVR P37/AN7 P36/AN6 P35/AN5 P34/AN4 P33/AN3 P32/AN2 P31/AN1 P30/AN0 P07/SCK P06/SO P05/SI P04/PWO P03/EC P02/ADST P01/BZ2 P00 P61/X1A P60/X0A P42 P41/INT1 P40/INT0 RST N.C. N.C. N.C. N.C. N.C. N.C. N.C. VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS
65 66 67 68 69 70 71 72 73 74 75 76 77 78
92 91 90 89 88 87 86 85 84 83 82 81 80 79
VCC A14 A13 A8 A9 A11 OE A10 CE O8 O7 O6 O5 O4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
(MDP-64C-P02)
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MB89910 Series
s PIN DESCRIPTION
Pin no. SH-DIP*1 26 27 20 19 24 QFP*2 20 21 14 13 18 MDIP*3 42 43 20 19 24 Pin name X0 X1 X0A/P60 X1A/P61 RST C I These pins can select either general-purpose CMOS inputs or subclock oscillator pins by the mask options. When these pins are used as a general-purpose input pin, the pin is a hysteresis input with a built-in noise canceller. Reset I/O pin This pin is an N-ch open-drain output type with pull-up resistor and a hysteresis input type. "L" is output from this pin by an internal source. The internal circuit is initialized by the input of "L". This pin is with a noise canceller. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as a buzzer output. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as the external activation pin for the A/D converter. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as the external clock input for the 16-bit timer/counter. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as the PWM output for the 8-bit PWM timer. General-purpose CMOS I/O ports These port inputs are a hysteresis input, with a built-in noise canceller. Also serve as serial data outputs for the 8-bit serial interface. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as the serial transfer clock output for the 8-bit serial interface. P-ch high-voltage open-drain output ports for large current Circuit type A Function Main clock crystal oscillator pins
18
12
18
P00
D
17
11
17
P01/BZ2
D
16
10
16
P02/ADST
D
15
9
15
P03/EC
D
14
8
14
P04/PWO
D
13, 12
7, 6
13, 12
P05/SI, P06/SO
D
11
5
11
P07/SCK
D
47 to 40
41 to 34
63 to 56
P10 to P17
G
*1: DIP-48P-M01 *2: FPT-48P-M15 *3: MDP-64C-P02
(Continued)
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MB89910 Series
(Continued)
Pin no. SH-DIP*
1
QFP*
2
MDIP*
3
Pin name P20 to P27 P30/AN0 to P33/AN3
Circuit type G H
Function P-ch high-voltage open-drain output ports for small current General-purpose N-ch open-drain I/O ports These port inputs are a hysteresis input, each with a built-in noise canceller. Although the pins are also serve as an analog inputs, an analog input does not pass through their noise cancellers. General-purpose CMOS I/O ports These port inputs are a hysteresis input, each with a built-in noise canceller. Although the pins are also serve as an analog inputs, an analog input does not pass through their noise cancellers. General-purpose CMOS I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as an external interrupt. External interrupt input passes through the noise canceller. General-purpose N-ch open-drain I/O port This port input is a hysteresis input, with a built-in noise canceller. Also serves as an external interrupt. External interrupt input passes through the noise canceller. General-purpose N-ch open-drain I/O port This port input is a hysteresis input, with a built-in noise canceller. P-ch high-voltage open-drain output ports for small current P-ch high-voltage open-drain output port for small current Also serves as a buzzer output. Operating mode selection pin Usually, connect to VSS directly. On the product with an EPROM, the pin is the VPP pin. Voltage supply pin connected to a pull-down resistor for ports 1, 2, and 5 In products without a pull-down resistor, in the MB89P915, and in the MB89PV910, this pin should be left open.
38 to 31 10 to 7
32 to 25 4 to 1
54 to 47 10 to 7
6 to 3
48 to 45
6 to 3
P34/AN4 to P37/AN7
F
23
17
23
P40/INT0
D
22
16
22
P41/INT1
E
21
15
21
P42
E
30 29
24 23
46 45
P50 P51/BZ1
G G
28
22
44
TEST
B
39
33
55
VFDP
--
*1: DIP-48P-M01 *2: FPT-48P-M15 *3: MDP-64C-P02
(Continued)
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MB89910 Series
(Continued)
Pin no. SH-DIP* 48 25 1 2
1
QFP* 42 19 43 44
2
MDIP* 64 32, 41 1 2
3
Pin name VCC VSS AVSS AVR
Circuit type -- -- -- -- Power supply pin
Function
Power supply (GND) pin A/D converter power supply pin Use this pin at the same voltage as VSS. A/D converter reference voltage input pin
*1: DIP-48P-M01 *2: FPT-48P-M15 *3: MDP-64C-P02
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MB89910 Series
* External EPROM pins (MDIP only) Pin no. MDIP* 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 * : MDP-64C-P02 Pin name VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O1 O2 O3 VSS O4 O5 O6 O7 O8 CE A10 OE A11 A9 A8 A13 A14 VCC I/O O O "H" level output pin Address output pins Function
I
Data input pins
O I
Power supply (GND) pin Data input pins
O O O O
ROM chip enable pin Outputs "H" during standby. Address output pin ROM output enable pin Outputs "L" at all times. Address output pin
O O O EPROM power supply pin
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MB89910 Series
s I/O CIRCUIT TYPE
Type A
X1 N-ch X0 P-ch
Circuit
Remarks * Main clock At an oscillation feedback resistor of approximately 1 M/5.0 V
Main clock control signal
B
C
R P-ch
* At an output pull-up resistor (P-ch) of approximately 50 k/5.0 V * CMOS hysteresis input (with a noise canceller)
N-ch
Hysteresis input (with a noise canceller)
D
P-ch
* CMOS I/O * CMOS hysteresis input (with a noise canceller)
N-ch
Hysteresis input (with a noise canceller)
E
* N-ch open-drain I/O * CMOS hysteresis input (with a noise canceller)
N-ch
Hysteresis input (with a noise canceller)
(Continued)
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MB89910 Series
(Continued)
Type F
P-ch
Circuit
Remarks * CMOS output * CMOS hysteresis input (with a noise canceller excluding analog inputs)
N-ch Port Hysteresis input (with a noise canceller) Analog input
G
P-ch
* P-ch high-voltage open-drain output * At an output pull-down resistor of approximately 100 k/5.0 V
VFDP
H
N-ch
* N-ch open-drain output * CMOS hysteresis input (with a noise canceller excluding analog inputs)
Hysteresis input (with a noise canceller) Analog input
I
Port X1A X0A Hysteresis input (with a noise canceller) N-ch P-ch
* Subclock The oscillation feedback resistor is built only in the MB89PV910. * CMOS hysteresis input (with a noise canceller) when no subclock is being used
Subclock control signal Port Hysteresis input (with a noise canceller)
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MB89910 Series
s HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on "1. Absolute Maximum Ratings" in section "s Electrical Characteristics" is applied between VCC and VSS. When latchup occurs, power supply current increases rapidly and might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings. Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and wake-up from stop mode.
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s PROGRAMMING TO EPROM ON THE MB89P915
The MB89P915 is an OTPROM version of the MP89910 series.
1. Features
* 16-Kbyte PROM on chip
2. Memory Space
Memory space in each mode such as 16-Kbyte PROM mode is diagrammed below.
MB89P915 0000H I/O 0080H RAM 0280H Not available 8000H Not available (Read value FFH) C000H Program area (PROM) 16 KB FFFFH
EPROM mode (Corresponding addresses on the EPROM programmer)
0000H Free space (Read value FFH) 4000H Program area (PROM) 16 KB 7FFFH
3. Programming to the EPROM
Since the MB89P915 requires a special method for programming to its PROM, the types of general-purpose EPROM programmers applicable to the MB89P915 are limited. Programming to the PROM on the MB89P915 requires an EPROM programmer applicable to the MB89P915 and a dedicated adapter. When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed as follows: * Programming procedure (1) Set the EPROM programmer to the MB89P195. (2) Load program data into the EPROM programmer at 4000H to 7FFFH. (note that addresses 0C000H to 0FFFFH in the operation mode correspond to 4000H to 7FFFH in EPROM mode.) (3) Program with the EPROM programmer.
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4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked OTPROM microcomputer program.
Program, verify
Aging +150C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature. For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Recommended programmer manufacturer and programmer name Part no. Package Compatible socket adapter Sun Hayato Co., Ltd. Data I/O Co., Ltd. UNISITE 3900 2900 (ver.5.0 or later) (ver.2.8 or later) (ver.3.8 or later) MB89P915P-SH SH-DIP-48 ROM-48QF2-28DP-8L Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403 FAX: (81)-3-5396-9106 Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444 EUROPE (49)-8-985-8580
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MB89910 Series
s PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20CZ
2. Programming Socket Adapter
Any special programming adapter is not required since the package for the EPROM to be used is DIP-28.
3. Memory Space
EPROM memory space and the memory space on the MB89PV910 are diagrammed below.
MB89PV910 0000H I/O 0080H RAM 0480H Not available 8000H 0000H Program area (EPROM) 32 KB 7FFFH MBM27C256A-20CZ
Program area 32 KB
FFFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A-20CZ. (2) Load program data into the EPROM programmer at 0000H to 7FFFH. (note that addresses 08000H to 0FFFFH in the operation mode correspond to 0000H to 7FFFH in the EPROM mode.) (3) Program with the EPROM programmer.
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s BLOCK DIAGRAM
X0 X1
Main clock oscillator
Timebase timer Reset circuit (Watchdog timer)
RST VFDP
Clock controller High-voltage output port 1 X0A/P60 X1A/P61 Port 6 Internal bus Subclock oscillator (32.768 kHz) 8
P10 to P17
High-voltage output port 2
8
P20 to P27
CMOS input port
High-voltage output port 5
P50
Watch prescaler Buzzer output
P51/BZ1
P01/BZ2 Low-voltage detection reset P02/ADST CMOS I/O port P00 P07/SCK P06/SO P05/SI Port 0
P30/AN0 to P33/AN3
Port 3
N-ch open-drain I/O port 8-bit serial I/O
4
AVR AVSS Port 3
8-bit A/D converter
8-bit PWM timer
P04/PWO
P34/AN4 to 4 P37/AN7
CMOS I/O port
16-bit timer/counter
P03/EC
RAM
N-ch open-drain output port Port 4 P42 P41/INT1 External interrupt Port 4 P40/INT0
F2MC-8L CPU
ROM CMOS I/O port Other pins VCC, VSS, TEST
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MB89910 Series
s CPU CORE
1. Memory Space
The microcontrollers of the MB89910 series offer a memory space of 64 Kbytes for storing all of I/O, data, and program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/O area. The data area can be divided into register, stack, and direct areas according to the application. The program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. * Memory Space
MB89P915 MB89915 0000 H I/O 0080 H RAM 1 KB 0100 H Register 0200 H 0200 H 0280 H 0480 H Not available 8000 H C000 H External ROM 32 KB E000 H ROM* 16 KB ROM 8 KB FFFF H Not available Not available 0100 H Register 0180 H 0080 H RAM 512 B 0100 H Register I/O 0080 H 0000 H I/O
MB89PV910 0000 H
MB89913
FFFF H
FFFF H
*: This is an internal PROM on the MB89P915.
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2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers in the memory. The following registers are provided: Program counter (PC): Accumulator (A): Temporary accumulator (T): Index register (IX): Extra pointer (EP): Stack pointer (SP): Program status (PS): A 16-bit register for indicating instruction storage positions A 16-bit temporary register for storing arithmetic operations, etc. When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register which performs arithmetic operations with the accumulator When the instruction is an 8-bit data processing instruction, the lower byte is used. A 16-bit register for index modification A 16-bit pointer for indicating a memory address A 16-bit register for indicating a stack area A 16-bit register for storing a register pointer, a condition code
16 bits PC A T IX EP SP PS : Program counter : Accumulator
Initial value FFFDH Indeterminate
: Temporary accumulator Indeterminate : Index register : Extra pointer : Stack pointer : Program status Indeterminate Indeterminate Indeterminate I-flag = 0, IL1, 0 = 11 The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for use as a condition code register (CCR). (See the diagram below.) * Structure of the Program Status Register
15 PS 14 13 RP 12 11 10 9 8 7 H 6 I 5 4 3 N 2 Z 1 V 0 C
Vacancy Vacancy Vacancy
IL1, 0
RP
CCR
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MB89910 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. * Rule for Conversion of Actual Addresses of the General-purpose Register Area
RP Lower OP codes b1 b0
"0" "0" "0" "0" "0" "0" "0" "1" R4 R3 R2 R1 R0 b2
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of CPU operations at the time of an interrupt. H-flag: Set to `1' when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. This flag is for decimal adjustment instructions. I-flag: IL1, 0: Interrupt is enabled when this flag is set to `1'. Interrupt is disabled when the flag is cleared to `0'. Cleared to `0' at the reset. Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is higher than the value indicated by this bit. IL1 0 0 1 1 IL0 0 1 0 1 Interrupt level 1 2 3 Low High-low High
N-flag: Set to `1' if the MSB becomes to `1' as the result of an arithmetic operation. Cleared to `0' when the bit is cleared to `0'. Z-flag: V-flag: Set to `1' when an arithmetic operation results in 0. Cleared to `0' otherwise. Set to `1' if the complement on 2 overflows as a result of an arithmetic operation. Cleared to to `0' if the overflow does not occur.
C-flag: Set to `1' when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to `0' otherwise. Set to the shift-out value in the case of a shift instruction.
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MB89910 Series
The following general-purpose registers are provided: General-purpose registers: An 8-bit resister for storing data The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains eight registers and up to a total of 32 banks can be used on the MB89915. The bank currently in use is indicated by the register bank pointer (RP). * Register Bank Configuration
This address = 0100H + 8 x (RP) R0 R1 R2 R3 R4 R5 R6 R7 32 banks Memory area
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MB89910 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (R/W) (R/W) (R/W) (R/W) SMR SDR ADC1 ADC2 (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) (R/W) (R/W) (R/W) (R) (R/W) (W) (W) (R/W) (R/W) (R/W) (R/W) SYCC STBC WDTC TBCR WPCR PDR3 DDR3 BUZR EIC PDR1 PDR2 PDR5 PDR6 PDR4 DDR4 COMR CNTR TMCR TCHR TCLR Read/write (R/W) (W) Register name PDR0 DDR0 Register description Port 0 data register Port 0 data direction register Vacancy Vacancy Vacancy Vacancy Vacancy System clock control register Standby control register Watchdog timer control register Time-base timer control register Watch prescaler control register Port 3 data register Port 3 direction register Buzzer register External interrupt control register Port 1 data register Port 2 data register Port 5 data register Port 6 data register Port 4 data register Port 4 direction register PWM compare register PWM control register 16-bit timer control register 16-bit timer control register (H) 16-bit timer control register (L) Vacancy Serial mode register Serial data register A/D converter control register 1 A/D converter control register 2
(Continued)
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MB89910 Series
(Continued)
Address 20H 21H 22H 23H 24H to 7BH 7CH 7DH 7EH 7FH Note: Do not use vacancies. (W) (W) (W) ILR1 ILR2 ILR3 (W) (R/W) PCR LVRC Read/write (R/W) Register name ADCD Vacancy Port input control register Low-voltage detection reset control register Vacancy Interrupt level setting register 1 Interrupt level setting register 2 Interrupt level setting register 3 Vacancy Register description A/D converter data register
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MB89910 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Parameter
Symbol VCC AVR
Value Min. VSS - 0.3 - 0.6 VCC - 40 VSS - 0.3 VSS - 0.3 VSS - 0.3 VCC - 40.0 Max. VSS + 7.0 13.0 VCC + 0.3 VCC + 0.3 7.0 VCC + 0.3 VCC + 0.3 -120 -90 -12 -20 -36 -6
Unit V V V V V V V mA mA mA mA mA mA
Remarks AVR VCC + 0.3*1
Power supply voltage
VPP VFDP VI1 VI2 VO1
Input voltage
Except P41*2 P41 Except P10 to P17, P20 to P27, P50, P51*2 P10 to P17, P20 to P27 P50, P51
Output voltage VO2 "H" level total maximum output current "H" level total average output current "H" level maximum output current IOH IOHAV
Average value (operating current x operating rate) P00 to P07, P34 to P37, P40 P20 to P27, P50, P51 P10 to P17 P00 to P07, P34 to P37, P40 Average value (operating current x operating rate) P20 to P27, P50, P51 Average value (operating current x operating rate) P10 to P17 Average value (operating current x operating rate)
IOH

"H" level average output current
IOHAV
-10
mA
"L" level total maximum output current "L" level total average output current "L" level maximum output current "L" level average output current IOL IOLAV IOL IOLAV
-20 36 20 10 4
mA mA mA mA mA
Average value (operating current x operating rate) P00 to P07, P30 to P37, P40 to P47
(Continued)
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MB89910 Series
(Continued)
(AVSS = VSS = 0.0 V)
Parameter Power consumption Operating temperature Storage temperature
Symbol PD TA Tstg
Value Min. -- -- -40 -55 Max. 440 360 +85 +150
Unit mW mW C C
Remarks SH-DIP: DIP-48-M01 QFP: FPT-48-M15
*1: Take care so that AVR does not exceed VCC + 0.3 V and VCC does not exceed VCC, such as when power is turned on. *2: VI and VO must not exceed VCC + 0.3 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Parameter
Symbol
Value Min. 4.5* Max. 5.5*
Unit
Remarks Normal operation assurance range* (MB89PV910) Normal operation assurance range* (MB89P915/915/913) Watch mode, sub-RUN mode Retains the RAM state in stop mode
V
Power supply voltage
VCC
3.8* 2.7 1.5
5.5* 5.5 5.5 VCC VCC + 0.3 +85
V V V V V C
A/D converter reference input voltage High-voltage pull-down resistor supply voltage Operating temperature
AVR VFDP TA
0.0 VCC - 35.0 -40
* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1 and "5. A/D Converter Electrical Characteristics."
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MB89910 Series
Figure 1
Operating Voltage vs. Main Clock Operating Frequency
6
5 Operation assurance range
Operating voltage (V)
4
3
2
1
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
2.0
1.3
1.0
0.8
0.66 0.57
0.5
0.44
0.4 (s)
Minimum execution time (instruction cycle)
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH. Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
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MB89910 Series
3. DC Characteristics
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name P00 to P07, P30 to P37, P40 to P42, P60, P61 X0, RST X1, TEST P00 to P07, P30 to P37, P40 to P42, P60, P61 X0, RST X1, TEST P30 to P33, P42 P41 P00 to P07, P30 to P37, P40 to P42, P60, P61 P20 to P27, P50, P51 P10 to P17 P00 to P07, P30 to P37, P40 to P42, P60, P61 RST, P00 to P07, P30 to P37, P40 to P42, P60, P61 P20 to P27, P50, P51 P10 to P17 RST, P10 to P17, P20 to P27, P50, P51
Condition
Value Min. Typ. Max.
Unit
Remarks
"H" level input voltage
VIHS
--
0.8 VCC
--
VCC + 0.3
V
"L" level input voltage
VILS
--
VSS - 0.3
--
0.2 VCC
V
Open-drain output pin application voltage
VD1 VD2
-- --
VSS - 0.3 VSS - 0.3
-- --
VCC + 0.3 7.0
V V Excluding P30 to P33 and P41, P42
VOH1 "H" level output voltage VOH2 VOH3 VOL1 VOL2 Input leakage current ILI1
IOH = -2.0 mA
2.4
--
--
V
IOH = -10 mA IOH = -20 mA IOL = 1.8 mA IOL = 4.0 mA 0 < VI < VCC
3.0 3.0 -- -- --
-- -- -- -- --
-- -- 0.4 0.6 5
V V V V A
"L" level output voltage
Output leakage ILO1 current ILO2 Pull-up resistance Pull-down resistance RPULL RPD
VI = VFDP VI = VFDP VIN = 0.0 V VIN = 5.0 V
-- -- 25 50
-- -- 50 100
-10 -20 100 150
A A k k
VFDP = VCC - 35.0 V VFDP = VCC - 35.0 V
Assuming the pulldown resistor option selected
(Continued)
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MB89910 Series
(Continued)
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name
Condition FCH = 8 MHz VCC = 5.0 V tinst*2 = 0.5 s when A/D conversion is stopped FCH = 8 MHz VCC = 3.8 V tinst*2 = 8.0 s when A/D conversion is stopped FCH = 8 MHz VCC = 5.0 V tinst*2 = 0.5 s when A/D conversion is stopped FCH = 8 MHz VCC = 3.8 V tinst*2 = 8.0 s when A/D conversion is stopped
Value Min. -- -- -- -- Typ. 10.0 9 3.0 1.8 Max. 18.0 15 6.0 2.4
Unit
Remarks
mA MB89P915 mA MB89913/ 915/PV910
ICC1
mA MB89P915 mA MB89913/ 915/PV910
ICC2
ICS1 Sleep mode
--
3
7
mA
Power supply current*1 When low-voltage ICS2 detection reset operation is enabled, ILVD is added to each ICSB power supply current.
--
1.2
1.8
mA
VCC
FCL = 32 kHz VCC = 3.0 V Subclock mode FCL = 32 kHz VCC = 3.0 V Subclock sleep mode FCL = 32 kHz VCC = 3.0 V * Watch mode * Main clock stop mode at dualclock system FCH = 8 MHz TA = +25C VCC = 5.0 V tinst*2 = 0.5 s when A/D conversion is activated
-- --
1.2 60
3.6 180
mA MB89P915 A MB89913/ 915/PV910
ICS3
--
32
64
A
ICCT
--
4
20
A
ICCA
--
12.5
22.5
mA
(Continued)
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MB89910 Series
(Continued)
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter
Symbol
Pin name
Condition FCL = 32.678 kHz, VCC = 3.0 V TA = +25C, * Subclock stop mode * Main clock stop mode at single clock system VCC = 5.0 V TA = +25C, * Subclock stop mode * Main clock stop mode at single clock system
Value Min. Typ. Max.
Unit
Remarks
ICCH
--
--
10
A
Power supply current*1 When low-voltage detection reset ILVD operation is enabled, ILVD is added to each power supply current. IR
VCC
--
60
120
A
Power consumption of low-voltage detection reset
AVR
FCH = 8 MHz, TA = +25C, when A/D conversion is activated FCH = 8 MHz, TA = +25C, when A/D conversion is stopped
--
200
--
A
IRH
AVR
--
--
10
A
Input capacitance
CIN
Other than AVSS, AVR, f = 1 MHz VCC, and VSS
--
10
--
pF
*1: The power supply current is measured at external clock. *2: For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
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MB89910 Series
4. AC Characteristics
(1) Reset Timing
(AVR = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter RST "L" pulse width RST noise limit width
Symbol tZLZH tZLNC
Condition -- --
Value Min. 48 tXCYL 30 Typ. -- 50 Max. -- 80
Unit ns ns
Remarks
Note: tXCYL is the oscillation period (1/FCH) to input to the X0.
tZLZH tZLNC RST 0.2 VCC 0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Power supply rising time Power supply cut-off time
Symbol tR tOFF
Condition -- --
Value Min. -- 1 Max. 50 --
Unit ms ms
Remarks Power-on reset function only Due to repeated operations
Note: Make sure that power supply rises within the selected oscillation stabilization time. If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended.
tR 2.0 V
tOFF
VCC
0.2 V 0.2 V 0.2 V
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MB89910 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Clock frequency Clock cycle time
Symbol Pin name Condition FCH FCL tXCYL tLXCYL PWH PWL PWHL PWLL tCR tCF X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0, X0A -- -- -- -- -- -- --
Value Min. 2 -- 125 -- 30 -- -- Typ. -- 32.768 -- 30.5 -- 15.2 -- Max. 8 -- 500 -- -- -- 10
Unit MHz kHz ns s ns
Remarks
Input clock pulse width
External clock s ns External clock
Input clock rising/falling time
* X0 and X1 Timing and Conditions
tXCYL PWH tCR 0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC tCF PWL
X0
0.2 VCC
* Main Clock Conditions
When a crystal or ceramic resonator is used
When an external clock is used
X0
X1
X0
X1 Open
C0
C1
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MB89910 Series
* X0A and X1A Timing and Conditions
tLXCYL PWHL tCR 0.8 VCC X0A 0.2 VCC 0.2 VCC 0.2 VCC 0.8 VCC tCF PWLL
* Subclock Conditions
When a crystal or ceramic resonator is used MB89PV910 X0A X1A When a crystal or ceramic resonator is used MB89913/915/P915 X0A X1A X0A X1A Open RF RD C0 C1 C0 C1
When an external clock is used
(4) Instruction Cycle Parameter Instruction cycle (minimum execution time) Symbol Value (typical) 4/FCH, 8/FCH, 16/FCH, 32/FCH tinst 2/FCL s Unit s Remarks Operation at FCH = 8 MHz; (4/FCH)tinst = 0.5 s Operation at FCL = 32.768 kHz; (4/FCH)tinst = 61.036 s
Note: When operating at 8 MHz, the cycle varies with the execution time.
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MB89910 Series
(5) Low-voltage Detection Reset
(AVSS = VSS 0.0 V, TA = -40C to +85C)
Parameter
Symbol VDL1
Condition -- -- -- -- -- -- -- -- -- -- --
Value Min. 3.00 3.30 3.70 3.10 3.40 3.80 0.10 0.3 16 tXCYL -- -- Max. 3.60 3.90 4.40 3.80 4.10 4.60 -- -- -- 2.0 0.10
Unit V V V V V V V s ns s V/s
Remarks
Detection voltage at power supply voltage fall
VDL2 VDL3 VDH1
Detection voltage at power supply voltage rise Hysteresis width Reset insensitive time Reset sensitive width Reset detection delay time Voltage regulation (V/t)
VDH2 VDH3 V tL tLW tD VCR
VDH and VDL are set for the MB89913/915 by mask options and for the MB89P915 by a register.
Power supply voltage VCC VDH V VDL
t V
tOSC RUN RESET
tD
tOSC
tD
tOSC oscillation stabilization time 218 = 32.8 ms (FCH = 8 MHz) Power supply voltage VCC VDH VDL
t L or less
t LW or less
t RUN RESET Reset not applied Reset applied t
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MB89910 Series
(6) Serial I/O Timing
(AVR = VCC = +5.0 V10%, AVSS = VSS= 0.0 V, TA = -40C to +85C)
Parameter Serial clock cycle time SCK SO time Valid SI SCK SCK valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SO time Valid SI SCK SCK valid SI hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
Pin name SCK SCK, SO SI, SCK SCK, SI SCK SCK SCK, SO SI, SCK SCK, SI
Condition
Value Min. 2 tinst* -200 1/2 tinst* 1/2 tinst* 1 tinst* 1 tinst* Max. -- 200 -- -- -- -- 200 -- --
Unit s ns s s s s ns s s
Remarks
Internal shift clock mode
External shift clock mode
0 1/2 tinst* 1/2 tinst*
* : For information on tinst, see "(4) Instruction Cycle."
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MB89910 Series
* Internal Shift Clock Mode
tSCYC SCK 2.4 V 0.8 V 0.8 V
tSLOV SO 2.4 V 0.8 V
tIVSH SI 0.8 VCC 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
* External Shift Clock Mode
tSLSH SCK 0.8 VCC 0.2 VCC 0.2 VCC
tSHSL
0.8 VCC
tSLOV SO 2.4 V 0.8 V
tIVSH 0.8 VCC SI 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
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MB89910 Series
(7) Peripheral Input Timing
(AVR = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" level pulse width Peripheral input "L" level pulse width
Symbol tILIH tIHIL
Pin name EC, ADST INT0, INT1 EC, ADST INT0, INT1
Condition
Value Min. Max. 2 tinst* -- --
Unit s s
Remarks
-- 2 tinst*
* : For information on tinst, see "(4) Instruction Cycle."
tIHIL INT0, INT1 EC ADST 0.2 VCC
tILIH
0.8 VCC 0.2 VCC
0.8 VCC
(8) Peripheral input noise limit width
(AVR = VCC = +5.0 V10%, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Peripheral input "H" level noise limit width 1
Symbol
Pin name All inputs excluding INT1 and INT0
Min. 7 15 7 15 30
Value Typ. 15 30 15 30 50 100 50 100
Max. 30 60 30 60 100 250 100 250
Unit ns ns ns ns ns ns ns ns
Remarks MB89PV910 MB89P915 MB89913/ 915 MB89PV910 MB89P915 MB89913/ 915 MB89PV910 MB89P915 MB89913/ 915 MB89PV910 MB89P915 MB89913/ 915
tIHNC1
Peripheral input "L" level noise limit width 1
tILNC1
All inputs excluding INT1 and INT0
Peripheral input "H" level noise limit width 2
tIHNC2
INT1, INT0 50 30
Peripheral input "L" level noise limit width 2
tILNC2
INT1, INT0 50
Note: The minimum rating is always cancelled, while values equal to or greater than maximum ratings are not cancelled.
P00 to P07, P30 to P37, P40 to P42, P60, P61, SCK, SI, EC INT0, INT1 ADST
tILNC1 tILNC2 0.8 VCC 0.2 VCC 0.2 VCC
tIHNC1 tIHNC2 0.8 VCC
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MB89910 Series
5. A/D Converter Electrical Characteristics
(VCC = +3.8 V to +5.5 V, F = 8 MHz, AVSS = VSS = 0.0 V, TA = -40C to +85C)
Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Interchannel disparity A/D mode conversion time Sense mode conversion time Analog port input current Analog input voltage Reference voltage Reference voltage supply current
Symbol Pin name
Condition
Value Min. -- -- -- -- Typ. -- -- -- -- Max. 8 3.0 1.0 0.9
Unit Remarks bit LSB LSB LSB mV
--
--
VOT VFST
AN0 to AN7 -- AN0 to AN7
AVSS - 1.5 LSB AVSS +0.5 LSB AVSS + 2.5 LSB AVR - 3.5 LSB -- AVR - 1.5 LSB -- 44 tinst* 12 tinst* -- -- -- 200
AVR +0.5 LSB mV 1.0 -- -- 10 AVR AVCC -- LSB s s A V V A
--
--
-- --
IAIN -- IR
AN0 to AN7 AVR = VCC = 5.0 V AN0 to AN7 AVR AVR -- AVR = 5.0 V
-- 0.0 3.4 --
* : For information on tinst, see "(4) Instruction Cycle" in "4. AC Characteristics."
6. A/D Converter Glossary
* Resolution Analog changes that are identifiable with the A/D converter When the number of bits is 8, analog voltage can be divided into 28 = 256. * Linearity error (unit: LSB) The deviation of the straight line drawn connecting the zero transition point ("0000 0000 " "0000 0001") with the full-scale transition point ("1111 1111 " "1111 1110") from actual conversion characteristics * Differential linearity error (unit: LSB) The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value * Total error (unit: LSB) The difference between theoretical and actual conversion values
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MB89910 Series
Digital output 1111 1111 * * * * * * * * * * * * * 0000 0000 0000 0010 0001 0000 VOT 1111 1110
Theoretical conversion value Actual conversion value
(1 LSB x N + VOT) 1 LSB = AVR 256 VNT - (1 LSB x N + VOT) 1 LSB V( N + 1 ) T - VNT - 1 1 LSB VNT - (1 LSB x N + 0.5 LSB) 1 LSB
Linearity error = Differential linearity error = Total error =
Linearity error
VNT V(N + 1)T
VFST
Analog input
7. Notes on Using A/D Converter
* Input impedance of the analog input pins The A/D converter used for the MB89910 series contains a sample hold circuit as illustrated below to fetch analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion. For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output impedance of the external circuit low. If a higher accurancy is required, set the output impedance in this series to 2 k or less. Note that if the impedance cannot be kept low output impedance, it is recommended either to use the software to continuously activate the A/D converter for simulating longer sampling time or to connect an external capacitor of approx. 0.1 F to the analog input pin. * Analog Input Equivalent Circuit
Analog input pin Comparator If the output impedance of external circuit is high, it is recommended to connect an external capacitor of approx. 0.1 F. . R = 6 k . Close for 8 instruction cycles after activating A/D conversion. Analog channel selector Sample hold circuit . C = 33 pF .
* Error The smaller the | AVR - AVSS |, the greater the error would become relatively.
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MB89910 Series
s EXAMPLE CHARACTERISTICS
(1) "L" Level Output Voltage (2) "H" Level Output Voltage
VOL vs. IOL VOL (V) TA = +25C 0.5 VCC = 3.0 V 0.4 0.3 0.2 0.1 0.0 VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V VCC = 2.5 V VCC - VOH (V) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) 0.0 0.0 -0.5
VCC - VOH vs. IOH TA = +25C VCC = 2.5 V
VCC = 3.0 V VCC = 4.0 V VCC = 5.0 V VCC = 6.0 V
-1.0
-1.5
-2.0
-2.5
-3.0 IOH (mA)
(3) "H" Level Input Voltage/"L" Level Input Voltage (Hysteresis Input)
CMOS hysteresis input VIN (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 7 VCC (V) VIHS VILS TA = +25C
VIHS: Threshold when input voltage in hysteresis characteristics is set to "H" level VILS: Threshold when input voltage in hysteresis characteristics is set to "L" level
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MB89910 Series
(4) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC ICC1,ICC2 (mA) 16 14 12 10 8 6 Divide by 64 (ICC2) 4 2 0 2.0 3.0 4.0 5.0 6.0 7.0 VCC (V) 0 2.0 3.0 1.0 2.0 FCH = 8 MHz TA = +25C Divide by 4 (ICC1) 3.0 ICS, ICS2 (mA) 4.0
ICS1 vs. VCC, ICS2 vs. VCC
FCH = 8 MHz TA = +25C Divide by 4 (ICS1)
Divide by 64 (ICS2)
4.0
5.0
6.0
7.0 VCC (V)
ICSB (A) 200 180 160 140 120 100 80 60 40 20 0 2.0 3.0
ICSB vs. VCC TA = +25C
ICS3 (A) 50
ICS3 vs. VCC TA = +25C
40
30
20
10
0 4.0 5.0 6.0 7.0 VCC (V) 2.0 3.0 4.0 5.0 6.0 7.0 VCC (V)
(Continued)
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MB89910 Series
(Continued)
ICCT (A) 36 32 28 24 20 16 12 8 4 0 2.0 3.0
ICCT vs. VCC
ICCH (A) 1.8 TA = +25C 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
ICCH vs. VCC
TA = +25C
4.0
5.0
6.0
7.0 VCC (V)
2.0
3.0
4.0
5.0
6.0
7.0 VCC (V)
(5) Pull-up Resistance
RPULL vs. VCC RPULL (k) 1,000 500
100 50 TA = +85C TA = +25C TA = -40C
10 1 2 3 4 5 6 7 VCC (V)
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MB89910 Series
s INSTRUCTIONS
Execution instructions can be divided into the following four groups: * * * * Transfer Arithmetic operation Branch Others
Table 1 lists symbols used for notation of instructions. Table 1 Symbol dir off ext #vct #d8 #d16 dir: b rel @ A AH AL T TH TL IX Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits) Immediate data (16 bits) Bit direct address (8:3 bits) Branch relative address (8 bits) Register indirect (Example: @A, @IX, @EP) Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of accumulator A (8 bits) Lower 8 bits of accumulator A (8 bits) Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.) Upper 8 bits of temporary accumulator T (8 bits) Lower 8 bits of temporary accumulator T (8 bits) Index register IX (16 bits) Instruction Symbols Meaning
(Continued)
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MB89910 Series
(Continued)
Symbol EP PC SP PS dr CCR RP Ri x (x) (( x )) Extra pointer EP (16 bits) Program counter PC (16 bits) Stack pointer SP (16 bits) Program status PS (16 bits) Accumulator A or index register IX (16 bits) Condition code register CCR (8 bits) Register bank pointer RP (5 bits) General-purpose register Ri (8 bits, i = 0 to 7) Indicates that the very x is the immediate data. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Indicates that the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) The address indicated by the contents of x is the target of accessing. (Whether its length is 8 or 16 bits is determined by the instruction in use.) Meaning
Columns indicate the following: Mnemonic: ~: #: Operation: TL, TH, AH: Assembler notation of an instruction Number of instructions Number of bytes Operation of an instruction A content change when each of the TL, TH, and AH instructions is executed. Symbols in the column indicate the following: * "-" indicates no change. * dH is the 8 upper bits of operation description data. * AL and AH must become the contents of AL and AH immediately before the instruction is executed. * 00 becomes 00. N, Z, V, C: OP code: An instruction of which the corresponding flag will change. If + is written in this column, the relevant instruction will change its corresponding flag. Code of an instruction. If an instruction is more than one code, it is written according to the following rule: Example: 48 to 4F This indicates 48, 49, ... 4F.
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MB89910 Series
Table 2 Mnemonic MOV dir,A MOV @IX +off,A MOV ext,A MOV @EP,A MOV Ri,A MOV A,#d8 MOV A,dir MOV A,@IX +off MOV A,ext MOV A,@A MOV A,@EP MOV A,Ri MOV dir,#d8 MOV @IX +off,#d8 MOV @EP,#d8 MOV Ri,#d8 MOVW dir,A MOVW @IX +off,A MOVW ext,A MOVW @EP,A MOVW EP,A MOVW A,#d16 MOVW A,dir MOVW A,@IX +off MOVW A,ext MOVW A,@A MOVW A,@EP MOVW A,EP MOVW EP,#d16 MOVW IX,A MOVW A,IX MOVW SP,A MOVW A,SP MOV @A,T MOVW @A,T MOVW IX,#d16 MOVW A,PS MOVW PS,A MOVW SP,#d16 SWAP SETB dir: b CLRB dir: b XCH A,T XCHW A,T XCHW A,EP XCHW A,IX XCHW A,SP MOVW A,PC ~ 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 # 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 Transfer Instructions (48 instructions) Operation (dir) (A) ( (IX) +off ) (A) (ext) (A) ( (EP) ) (A) (Ri) (A) (A) d8 (A) (dir) (A) ( (IX) +off) (A) (ext) (A) ( (A) ) (A) ( (EP) ) (A) (Ri) (dir) d8 ( (IX) +off ) d8 ( (EP) ) d8 (Ri) d8 (dir) (AH),(dir + 1) (AL) ( (IX) +off) (AH), ( (IX) +off + 1) (AL) (ext) (AH), (ext + 1) (AL) ( (EP) ) (AH),( (EP) + 1) (AL) (EP) (A) (A) d16 (AH) (dir), (AL) (dir + 1) (AH) ( (IX) +off), (AL) ( (IX) +off + 1) (AH) (ext), (AL) (ext + 1) (AH) ( (A) ), (AL) ( (A) ) + 1) (AH) ( (EP) ), (AL) ( (EP) + 1) (A) (EP) (EP) d16 (IX) (A) (A) (IX) (SP) (A) (A) (SP) ( (A) ) (T) ( (A) ) (TH),( (A) + 1) (TL) (IX) d16 (A) (PS) (PS) (A) (SP) d16 (AH) (AL) (dir): b 1 (dir): b 0 (AL) (TL) (A) (T) (A) (EP) (A) (IX) (A) (SP) (A) (PC) TL - - - - - AL AL AL AL AL AL AL - - - - - - - - - AL AL AL AL AL AL - - - - - - - - - - - - - - - AL AL - - - - TH - - - - - - - - - - - - - - - - - - - - - AH AH AH AH AH AH - - - - - - - - - - - - - - - - AH - - - - AH - - - - - - - - - - - - - - - - - - - - - dH dH dH dH dH dH dH - - dH - dH - - - dH - - AL - - - dH dH dH dH dH NZVC ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++-- ++-- ++-- ++-- ++-- ++-- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ++++ ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- OP code 45 46 61 47 48 to 4F 04 05 06 60 92 07 08 to 0F 85 86 87 88 to 8F D5 D6 D4 D7 E3 E4 C5 C6 C4 93 C7 F3 E7 E2 F2 E1 F1 82 83 E6 70 71 E5 10 A8 to AF A0 to A7 42 43 F7 F6 F5 F0
Notes: * During byte transfer to A, T A is restricted to low bytes. * Operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (Reverse arrangement of F2MC-8 family)
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MB89910 Series
Table 3 Mnemonic ADDC A,Ri ADDC A,#d8 ADDC A,dir ADDC A,@IX +off ADDC A,@EP ADDCW A ADDC A SUBC A,Ri SUBC A,#d8 SUBC A,dir SUBC A,@IX +off SUBC A,@EP SUBCW A SUBC A INC Ri INCW EP INCW IX INCW A DEC Ri DECW EP DECW IX DECW A MULU A DIVU A ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A,#d8 CMP A,dir CMP A,@EP CMP A,@IX +off CMP A,Ri DAA DAS XOR A XOR A,#d8 XOR A,dir XOR A,@EP XOR A,@IX +off XOR A,Ri AND A AND A,#d8 AND A,dir ~ 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 # 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 Arithmetic Operation Instructions (62 instructions) Operation (A) (A) + (Ri) + C (A) (A) + d8 + C (A) (A) + (dir) + C (A) (A) + ( (IX) +off) + C (A) (A) + ( (EP) ) + C (A) (A) + (T) + C (AL) (AL) + (TL) + C (A) (A) - (Ri) - C (A) (A) - d8 - C (A) (A) - (dir) - C (A) (A) - ( (IX) +off) - C (A) (A) - ( (EP) ) - C (A) (T) - (A) - C (AL) (TL) - (AL) - C (Ri) (Ri) + 1 (EP) (EP) + 1 (IX) (IX) + 1 (A) (A) + 1 (Ri) (Ri) - 1 (EP) (EP) - 1 (IX) (IX) - 1 (A) (A) - 1 (A) (AL) x (TL) (A) (T) / (AL),MOD (T) (A) (A) (T) (A) (A) (T) (A) (A) (T) (TL) - (AL) (T) - (A) CA C A (A) - d8 (A) - (dir) (A) - ( (EP) ) (A) - ( (IX) +off) (A) - (Ri) Decimal adjust for addition Decimal adjust for subtraction (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) TL - - - - - - - - - - - - - - - - - - - - - - - dL - - - - - - - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - - - - - - - 00 - - - - - - - - - - - - - - - - - - - - - - - AH - - - - - dH - - - - - - dH - - - - dH - - - dH dH 00 dH dH dH - - - - - - - - - - - - - - - - - - - - NZVC ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++++ +++- ---- ---- ++-- +++- ---- ---- ++-- ---- ---- ++R- ++R- ++R- ++++ ++++ ++-+ ++-+ ++++ ++++ ++++ ++++ ++++ ++++ ++++ ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- OP code 28 to 2F 24 25 26 27 23 22 38 to 3F 34 35 36 37 33 32 C8 to CF C3 C2 C0 D8 to DF D3 D2 D0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1F 84 94 52 54 55 57 56 58 to 5F 62 64 65
(Continued)
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MB89910 Series
(Continued)
Mnemonic AND A,@EP AND A,@IX +off AND A,Ri OR A OR A,#d8 OR A,dir OR A,@EP OR A,@IX +off OR A,Ri CMP dir,#d8 CMP @EP,#d8 CMP @IX +off,#d8 CMP Ri,#d8 INCW SP DECW SP ~ 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 # 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 Operation (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (A) (AL) (TL) (A) (AL) d8 (A) (AL) (dir) (A) (AL) ( (EP) ) (A) (AL) ( (IX) +off) (A) (AL) (Ri) (dir) - d8 ( (EP) ) - d8 ( (IX) + off) - d8 (Ri) - d8 (SP) (SP) + 1 (SP) (SP) - 1 Table 4 Mnemonic BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel BGE rel BBC dir: b,rel BBS dir: b,rel JMP @A JMP ext CALLV #vct CALL ext XCHW A,PC RET RETI ~ 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 # 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 TL - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - - NZVC ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++R- ++++ ++++ ++++ ++++ ---- ---- OP code 67 66 68 to 6F 72 74 75 77 76 78 to 7F 95 97 96 98 to 9F C1 D1
Branch Instructions (17 instructions) Operation TL - - - - - - - - - - - - - - - - - TH - - - - - - - - - - - - - - - - - AH - - - - - - - - - - - - - - dH - - NZVC ---- ---- ---- ---- ---- ---- ---- ---- -+-- -+-- ---- ---- ---- ---- ---- ---- Restore OP code FD FC F9 F8 FB FA FF FE B0 to B7 B8 to BF E0 21 E8 to EF 31 F4 20 30
If Z = 1 then PC PC + rel If Z = 0 then PC PC + rel If C = 1 then PC PC + rel If C = 0 then PC PC + rel If N = 1 then PC PC + rel If N = 0 then PC PC + rel If V N = 1 then PC PC + rel If V N = 0 then PC PC + reI If (dir: b) = 0 then PC PC + rel If (dir: b) = 1 then PC PC + rel (PC) (A) (PC) ext Vector call Subroutine call (PC) (A),(A) (PC) + 1 Return from subrountine Return form interrupt Table 5
Other Instructions (9 instructions) Operation TL - - - - - - - - - TH - - - - - - - - - AH - dH - - - - - - - NZVC ---- ---- ---- ---- ---- ---R ---S ---- ---- OP code 40 50 41 51 00 81 91 80 90
Mnemonic PUSHW A POPW A PUSHW IX POPW IX NOP CLRC SETC CLRI SETI
~ 4 4 4 4 1 1 1 1 1
# 1 1 1 1 1 1 1 1 1
47
48
3 PUSHW A SETC CLRB BBC INCW DECW MOVW MOVW dir: 1 dir: 1,rel SP SP SP,A A,SP A A,ext POPW MOV MOVW CLRI A,PS SETI CLRB BBC INCW DECW JMP MOVW dir: 0 dir: 0,rel A A @A A,PC 4 5 6 7 8 9 A B C D E F XCH A A XOR AND OR DAA A,#d8 A,#d8 A,#d8 DAS XCHW XORW ANDW ORW A, T A A A A, T A A A XOR AND OR MOV MOV CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 2 dir: 2,rel IX IX IX,A A,IX MOVW MOVW CLRB BBC INCW DECW MOVW MOVW @A,T A,@A dir: 3 dir: 3,rel EP EP EP,A A,EP CLRB BBC MOVW MOVW MOVW XCHW dir: 4 dir: 4,rel A,ext ext,A A,#d16 A,PC CMP @EP,#d8 CLRB BBC MOVW MOVW MOVW XCHW dir: 7 dir: 7,rel A,@EP @EP,A EP,#d16 A,EP DEC R0 DEC R1 DEC R2 DEC R3 DEC R4 DEC R5 DEC R6 DEC R7 R7 R6 CALLV #7 R5 CALLV #6 BLT rel R4 CALLV #5 BGE rel R3 CALLV #4 BZ rel R2 CALLV #3 BNZ rel R1 CALLV #2 BN rel R0 CALLV #1 BP rel CALLV #0 BC rel BNC rel
L
H
0
1
2
0
NOP
SWAP
RET
RETI
1
MULU
DIVU
A
A
JMP CALL PUSHW POPW MOV MOVW CLRC addr16 addr16 IX IX ext,A PS,A
2
ROLC
CMP
ADDC
SUBC
A
A
A
3
RORC
CMPW
ADDCW
SUBCW
MB89910 Series
A
A
A
4
MOV CMP ADDC SUBC A,#d8 A,#d8 A,#d8 A,#d8
5
MOV
CMP
A,dir
A,dir
ADDC SUBC MOV XOR AND OR MOV CMP CLRB BBC MOVW MOVW MOVW XCHW A,dir A,dir dir,A A,dir A,dir A,dir dir,#d8 dir,#d8 dir: 5 dir: 5,rel A,dir dir,A SP,#d16 A,SP
6
CMP CLRB BBC MOVW MOVW MOVW XCHW MOV CMP ADDC SUBC MOV XOR AND OR MOV dir: 6 dir: 6,rel A,@IX +d @IX +d,A IX,#d16 A,IX A,@IX +d A,@IX +d A,@IX +d A,@IX +d @IX +d,A @A,IX +d A,@IX +d A,@IX +d @IX +d,#d8 @IX +d,#d8
7
MOV CMP ADDC SUBC MOV XOR AND OR MOV A,@EP A,@EP A,@EP A,@EP @EP,A A,@EP A,@EP A,@EP @EP,#d8
8
MOV
CMP
A,R0
A,R0
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R0 A,R0 R0,A A,R0 A,R0 A,R0 R0,#d8 R0,#d8 dir: 0 dir: 0,rel
9
MOV
CMP
A,R1
A,R1
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R1 A,R1 R1,A A,R1 A,R1 A,R1 R1,#d8 R1,#d8 dir: 1 dir: 1,rel
A
MOV
CMP
A,R2
A,R2
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R2 A,R2 R2,A A,R2 A,R2 A,R2 R2,#d8 R2,#d8 dir: 2 dir: 2,rel
B
MOV
CMP
A,R3
A,R3
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R3 A,R3 R3,A A,R3 A,R3 A,R3 R3,#d8 R3,#d8 dir: 3 dir: 3,rel
C
MOV
CMP
A,R4
A,R4
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R4 A,R4 R4,A A,R4 A,R4 A,R4 R4,#d8 R4,#d8 dir: 4 dir: 4,rel
D
MOV
CMP
A,R5
A,R5
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R5 A,R5 R5,A A,R5 A,R5 A,R5 R5,#d8 R5,#d8 dir: 5 dir: 5,rel
E
MOV
CMP
A,R6
A,R6
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R6 A,R6 R6,A A,R6 A,R6 A,R6 R6,#d8 R6,#d8 dir: 6 dir: 6,rel
F
MOV
CMP
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A,R7
A,R7
ADDC SUBC MOV XOR AND OR MOV CMP SETB BBS INC A,R7 A,R7 R7,A A,R7 A,R7 A,R7 R7,#d8 R7,#d8 dir: 7 dir: 7,rel
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MB89910 Series
s INSTRUCTION MAP
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MB89910 Series
s MASK OPTIONS
Part number No. Specifying procedure Selection either single or dual clock Single-clock mode Dual-clock mode Pull-down resistors P17 to P10 P27 to P20 P51, P50 MB89PV910 -101 -102 MB89913 MB89915 MB89P915 -101 -102
Setting not Setting not Specify when Setting not Setting not possible possible ordering masking possible possible Single clock Dual clock Selectable Single clock Dual clock
1
2
All pins fixed to without pull-down resistor
Can be selected per pin.
All pins fixed to without pull-down resistor
3
Voltage to be detected for lowvoltage detection reset 3.3 0.3 V Cannot be used. 3.6 0.3 V 4.0 0.3 V
Selectable
Can be set by register.
s ORDERING INFORMATION
Part number MB89913P-SH MB89915P-SH MB89P915P-101-SH MB89P915P-102-SH MB89913PF MB89915PF MB89P915PF-101 MB89P915PF-102 MB89PV910C-101-ES-SH MB89PV910C-102-ES-SH Package 48-pin Plastic SH-DIP (DIP-48P-M01) Remarks
48-pin Plastic QFP (FPT-48P-M15) 64-pin Ceramic MDIP (MDP-64C-P02)
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MB89910 Series
s PACKAGE DIMENSIONS
48-pin Plastic SH-DIP (DIP-48P-M01)
43.69 -0.30 +.008 1.720 -.012
+0.20
INDEX-1 13.800.25 (.543.010) INDEX-2
5.25(.207) MAX 3.00(.118) MIN
+0.50
0.51(.020)MIN 0.250.05 (.010.002)
1.00 -0 +.020 .039 -0 1.7780.18 (.070.007) 1.778(.070) MAX
0.450.10 (.018.004)
15.24(.600) TYP
15MAX
40.894(1.610)REF
C
1994 FUJITSU LIMITED D48002S-3C-3
Dimensions in mm (inches)
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MB89910 Series
(Continued)
48-pin Plastic QFP (FPT-48P-M15)
15.300.40 SQ (.602.016) +0.30 12.00 -0.10 SQ +.012 .472 -.004 2.70(.106)MAX 0.05(.002)MIN (STAND OFF)
25
36
37
24
Details of "A" part 0.15(.006) 8.80 (.346) REF
13.600.40 (.535.016)
0.20(.008) 0.15(.006)MAX 0.50(.020)MAX
INDEX
48
"A"
13
Details of "B" part LEAD No.
1 12
0.80(.0315)TYP
0.300.06 (.012.002) "B"
0.16(.006)
M
0.15 -0.01 +.002 .006 -.0004 0.850.30 (.033.012)
+0.05
0~10
0.10(.004)
C
1994 FUJITSU LIMITED F48025S-1C-1
Dimensions in mm (inches)
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MB89910 Series
(Continued)
64-pin Ceramic MDIP (MDP-64C-P02)
56.900.64 (2.240.025) 0~9
15.24(.600) TYP
18.750.30 (.738.012)
19.050.30 (.750.012)
INDEX AREA
2.540.25 (.100.010) 33.02(1.300)REF
0.250.05 (.010.002)
10.16(.400)MAX
1.270.25 (.050.010)
1.7780.25 (.070.010)
0.46 -0.08 +.005 .018 -.003 55.12(2.170)REF
+0.13
0.900.13 (.035.005)
3.430.38 (.135.015)
C
1994 FUJITSU LIMITED M64002SC-1-4
Dimensions in mm (inches)
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MB89910 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281 0770 Fax: (65) 281 0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9703 (c) FUJITSU LIMITED
Printed in Japan
56

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